1. Field of Invention
The invention relates to a wafer level chip scale packaging structure and the method of fabricating the same. In particular, the invention relates to a wafer level chip scale packaging structure that uses a specially designed sacrificial layer material, interface crashes, or the elasticity of a suspension structure to remove the stress generated due to differential thermal expansion coefficients between the silicon (Si) wafer and the printed circuit board (PCB).
2. Related Art
The wafer level chip scale packaging is a very important technique for the packaging of wafers and PCB. The main difference from the conventional flip chip in package technique is: as the thermal expansion coefficients between the wafer (Si) and the PCB material is very large, it is likely to have some cracks at the solder ball joints during the reliability test after the wafer is assembled.
Therefore, one usually includes an underfill step in the technique of flip chip in package to protect the solder ball joint from being damaged. However, the underfill step is very time-consuming and it is very hard to repair once the process is completed. Therefore, the wafer level chip scale packaging is developed to replace the conventional flip chip in package technique. Since this kind of wafer level chip scale packaging techniques has superior electrical performance and lower manufacturing costs than other packaging forms and belongs to re-workable packaging techniques, it will play an important role in the production of future electronics.
We describe the developed wafer level chip scale packaging techniques in the following paragraphs. FIG. 1 shows the packaging structure disclosed by the Japanese Hitachi, Ltd in Electronic Components and Technology Conference (p. 40 to p. 46) in 2001. This technique is used in the packaging of Si wafer 10 and organic PCB 20. Its main spirit is to put an extremely soft elastic layer 40 at the bottom of the solder ball 30. The elastic layer 40 releases the stress generated due to the differential thermal expansion coefficients between the Si wafer 10 and the organic PCB 20. However, there are not many choices suitable for the elastic layer 40. It has its technical bottleneck in manufacturing. Therefore, its applications are limited to the packaging of integrated circuits (IC) with a wide pitch (low number of pins).
FIG. 2 shows a chip-scale carrier for semiconductor devices including mounted spring contacts disclosed in the U.S. Pat. No. 6,023,103. The technique uses an elastic metal wire 50 as the channel connecting a Si wafer 10 and an organic PCB 20. Using the elasticity of the metal wire 50, the stress generated by the differential thermal expansion coefficients between the Si wafer 10 and the organic PCB 20 can be removed. However, the metal wire is formed by bonding. To enhance its strength, one has to employ a special process to strengthen the metal. This inevitably increases the manufacturing cost.
FIG. 3 shows the Super CSP structure proposed by Fujitsu, Ltd. The technique uses a semiconductor process to grow a copper post 60 of about 100 micrometer high as the electrical contact between the Si wafer 10 and the organic PCB 20. However, using this structure to alleviate the stress is not perfect. Moreover, to grow such a copper post 60 and to protect the copper from being oxidized will increase the cost. Therefore, it is not practical.
FIG. 4 shows the wafer level packaging structure disclosed in the U.S. Pat. Application No. 2002/0127768 A1. Its main technical feature is to form a vent hole 80 below a conductive bump 70. Using the vent hole 80 to replace the elastic layer 40 in FIG. 1 can obtain a better elastic effect. However, the vent hole 80 requires a special material and an accompanying fabricating process. Therefore, it has some limitation in mass production.
In considering the reliability of the products, most packaging techniques can be applied to IC elements with a small pin number (smaller than 100 I/O ports) and area and cannot be used for future IC elements with a large pin number and area.
Therefore, for an optimized packaging (such as wafer level packaging) of future electronic devices that have a larger pin number, many functions, and a large chip size (such as system of single chip or system packaging), it is imperative to find a method to minimize the manufacturing cost and the packaging volume/surface.